The present invention relates to circuits for multiplying numbers in an electronic computer and in particular to a circuit for providing high-efficiency floating-point multiplication.
Electronic computers often represent numbers in a floating-point format. The floating-point format supports a larger range of numbers than can be provided for integer representations and conveniently permits the expression of fractional values, both of these benefits being obtained at the loss of some precision.
Generally, the floating-point format separately provides a sign bit (positive or negative), exponent bits (defining a base 2 exponent) and significand or mantissa bits. The general representation of a floating-point number will therefore be in the form:(−1)sign*significand*2exponent  (1)
A common standard for floating-point representation is provided by IEEE standard 754 hereby incorporated by reference. The common single precision floating-point format under this standard employs 32 bits and, proceeding from left (MSB) to right (LSB), allotting a single bit to the sign, eight bits to the exponent, and 23 bits to the significand, the latter of which includes an implicit left most significant bit 24 which is always one for a large class of floating-point numbers, known as normalized floating-point numbers. The normalization (left justification) of the significand in these numbers removes all the leading zeros from the significand. The leading one thus need not be stored. Floating-point numbers whose left most significand bit 24 is not one are known as subnormals. Subnormals are encountered infrequently in applications, and are particularly rare in pixel processing applications.
High-performance computer architectures provide specialized circuitry for processing floating-point calculations, for example, in the form of a floating-point fused multiply-add (FMA) unit which performs the general calculation of:A*B+C  (2)
Such circuits normally provide separate processing paths for the exponent and significand data. The exponent processing path requires simple logic blocks like small adders and comparators. The significand processing path requires complex logic that can have considerably longer processing time and consumes more power. For example, multiplication of the significands can be implemented using complex but high-speed significand multiplier circuit providing multiple stages of shifters and accumulators or architectures such as Wallace trees or Dadda multipliers.
An important task of many modern processors, and in particular portable devices such as cell phones and tablets, is processing of images comprised of pixel data. Pixel data is typically composed of one or more color channels, such as reg, green blue and alpha. The data values for each of these channels are relatively constrained, for example, having only positive values from 0 to 255 for an 8-bit per channel image format. Pixel data appears to be of the type that might be readily handled by integer arithmetic, but the need for sophisticated image processing normally requires floating-point operations, for example, for the application of filters and blending algorithms which apply non-integer weights. Such floating-point operations often must be repeated for millions of pixels.
The energy consumed by floating-point processors in common image-centric applications for portable devices such as cell phones and tablets can significantly affect the amount of time that the device can operate between battery chargings.